MISC — Minimal Instruction Set Computer

MISC is an experimental 8-bit CPU architecture with a 16-bit address space, designed around an intentionally restrictive instruction encoding.

Each instruction begins with a single-byte opcode, divided into a 3-bit addressing mode and a 5-bit instruction identifier. This limits the architecture to 8 addressing modes and 32 instructions. Additional operand bytes permit variable-length instructions.

The goal is to explore how capable a small processor can be within these constraints, while maintaining a relatively simple and well-defined architecture.

MISC is primarily a hobby engineering project, though its limited instruction set and straightforward design may also make it useful as an introductory CPU emulation exercise.

Reference Implementation

This repository contains an interpreter-style reference implementation written in Odin.

The interpreter serves primarily as a tool for developing, testing, and refining the MISC instruction set architecture. It is not intended to model any particular physical implementation, provide cycle-accurate emulation, or demonstrate an optimized emulator design.

The architecture and reference implementation are under active development and subject to change.

Specifications

• MISC Architecture Specification v0.3 — Defines the instruction set, registers, addressing modes, and architectural behavior.
• MISC Standard Host Interface v0.1 — Proposes optional conventions for interaction between MISC implementations and their host environments.

The ISA specification defines the processor itself. The Standard Host Interface is optional and is not required for ISA conformance.

Notes

The implementation and testing strategies here are intentionally "brute force". As this is a reference implementation for an ISA I'm stil designing, I am intentionally eschewing any kind of optimizations or cleverness in how this interpreter is written. As well, the "interpreter-style" implementation was chosen for ease of testing.